With the ever decreasing sizes of individual transistors on an MOS IC and the corresponding decrease in the thickness of the gate dielectric (typically an oxide of silicon), ESD protection is increasingly an important factor in determining the reliability and mean time between failure (MTBF) of an IC. In particular, as dielectric thickness decreases, the minimum voltage at which the dielectric will rupture also decreases. For example, conventional MOS type gate dielectrics employ about 500 to 1,000 Angstroms of silicon dioxide which ruptures at 6 to 9 volts per 100 Angstroms. Thus, 30 volts across a 500 Angstrom oxide dielectric could destroy the dielectric.
In addition to oxide rupture, ESD currents on the order of an ampere often appear at the IC input/output (I/O) pads. If the heat generated by these currents is not properly dissipated, electromigration of the metal in the lead pattern and microdiffusion of dopants in the IC can occur. The result is a short between the IC's substrate region and the lead pattern.
Generally an MOS type IC is most susceptible to ESD damage during assembly, test, transfer and installation when the voltage generated by a person handling the IC discharges across the IC's I/O pads. A person can easily develop 1,000 to 10,000 volts. The destructive effect of this high-voltage when discharged across an IC is partially alleviated by the source resistance of the human body. However, the resulting ESD signal can still be very damaging. To prevent dielectric rupture, a protection device for dissipating ESD energy is conventionally connected between each I/O pad of an MOS IC and the IC's internal circuitry.
ESD which can damage an IC can also occur during use. Therefore, ESD protection devices are always required on the input/output (I/O) pads of an IC to protect it from ESD damage.
U.S. Pat. No. 4,786,956 entitled "Input Protection Device for Integrated Circuits" discloses examples of prior art ESD protection devices.
In production, it is important to subject batches of different ICs to an ESD test. ESD testing ensures that the ESD protected ICs that do pass the ESD test will be able to sustain electrostatic discharges within a specified voltage and current range without failure. For example, to simulate electrostatic discharges from a common source, such as a human body, an external 100 pF capacitor is repetitively charged to ever increasing test voltages and discharged through a 1500 Ohm resistor into the I/O pads. These test voltages generally range from 500 V to 5000 V in 500 V increments.
Typically there are four ESD tests conducted during an ESD valuation:
1) positive test voltages with respect to V.sub.SS (ground), i.e. positive against V.sub.SS, PA1 2) negative test voltages with respect to V.sub.SS, i.e. negative against V.sub.SS, PA1 3) positive test voltages with respect to V.sub.CC, (supply voltage), i.e. positive against V.sub.CC, and PA1 4) negative test voltages with respect to V.sub.CC, i.e. negative against V.sub.CC.
For example, in the first test (the positive test voltages with respect to ground) a test probe is placed on the ground pad or pads and a positive voltage relative to the ground pads is then applied in sequence to each of the other pads on the IC. The other tests are conducted in a similar manner with a test probe placed on the appropriate pad containing V.sub.SS or V.sub.CC and a positive or negative voltage then applied in sequence to each of the other pads on the IC.
In the case of the commonly used NMOS and/or N-field transistor (N-channel transistor with field oxide gate insulation) based ESD protection devices, the most critical tests, i.e. when the ESD protection devices are most vulnerable, are positive against V.sub.SS and positive against V.sub.CC. This is because a conventional NMOS transistor comprises N-type source/drain regions in a P-type substrate or well thereby forming two NP junctions, i.e., between N-type source and P-type substrate, and N-type drain and P-type substrate, respectively. In order to prevent the two NP junctions from conducting when the transistor is in normal operation, the P-type substrate is generally coupled to a slightly negative voltage source with respect to V.sub.SS, for example, V.sub.SS -3 V.
However when the N-type drain is subjected to a high negative voltage, e.g. -5 kV, with respect to either V.sub.CC or V.sub.SS, the drain/substrate NP junction becomes forward biased and turns on in a manner similar to an NP diode junction. Conversely when a high positive voltage, e.g. 5 kV, with respect to V.sub.CC or V.sub.SS is applied to the N-type drain, despite the fact that the P-type substrate is coupled to a slightly negative voltage source with respect to V.sub.SS, because of the high positive voltage applied to the N-type source, the NP junction formed between the N-type source and the P-type substrate becomes reverse biased and breaks down.
As is well known in the art, an NP junction subject to a high negative voltage, i.e. forward biased, is less likely to be damaged when when the same NP junction is reverse biased, i.e. the NP junction is subjected to a high negative voltage which causes the NP junction to break down.
Hence a high negative voltage turns on the NMOS/N-field FET of an ESD protection device in a forward bias mode, typically when -10 to -30 volts or more, is applied across the drain or source NP junction. Conversely, a high positive voltage, typically +15 volts or more, applied across the same NP junction turns on the NMOS/N-field FET in a break-down mode. As such, while ESD protection devices based on N-type transistors, can generally sustain up to a 5 kV forward bias across their NP junction(s) without damage, the same NP junction(s) are vulnerable to positive voltage ESD discharges (i.e. NP junctions back biased) of the same magnitude.
Further, current flow through an ESD protection device is generally not uniform, i.e. current flow is not uniform across the active region of a typical MOS transistor. As a result, high power density can be localized in areas oil the transistor where there is high current, increasing the potential for localized ESD damage such as shorts between the substrate and lead pattern described above.
FIG. 1a shows a conventional method of providing ESD protection for an I/O pad 11 using an input ESD protection device 50 comprising an N-field transistor T1, a resistor 12, and a grounded gate NMOS transistor T2. Although resistor 12 is optional, it improves the ESD characteristics of input buffer 10 by introducing a voltage drop between pad 11 and buffer 10 thereby reducing the magnitude of the test voltage at the input node of buffer 11. As discussed above, because transistors T1 and T2 are both N-channel transistors, they can withstand the two negative voltage ESD tests without damage by operating in their forward biased mode.
During the positive against V.sub.SS ESD test, a large positive voltage to simulate an electrostatic discharge is applied to pad 11 causing N-field transistor T1 to break down. Being closest to input pad 11, N-field transistor T1 provides a primary current path to ground (V.sub.SS) for the electrostatic discharge, thereby avoiding a large current surge at the input of buffer 10. Grounded gate (gate G2 is grounded) N-channel transistor T2 further protects the input of buffer driver 10 and the IC's internal circuitry (not shown) coupled to the output of buffer driver 10, by providing a secondary current path to V.sub.SS for the ESD discharge. Transistor T2 also operates in the undesirable breakdown mode. As such, ESD protection device 50 is vulnerable to the positive against V.sub.SS ESD test.
During the positive against V.sub.CC ESD test, since transistor T1 is not coupled to V.sub.CC, i.e. none of the nodes of transistor T1 is directly coupled to V.sub.CC, there is no direct path between drain D1 of transistor T1 and V.sub.CC for current from the ESD test to flow. As such, transistor T1 cannot efficiently conduct the ESD test current to V.sub.CC. Instead, the ESD current has to take an indirect path to V.sub.CC, for example, via source S1 (only coupled directly to V.sub.SS), causing transistor T2 (also only coupled directly to V.sub.SS) to absorb more energy while operating in its undesirable breakdown mode. Hence, ESD protection device 50 is most vulnerable to the positive against V.sub.CC ESD test. Further, device 50 also uses two transistors T1 and T2 for operation.
In one variation of ESD protection device 50, N-field transistor T1 is replaced by a large NMOS transistor with an extended active area, i.e. with an extended N-channel. Such an ESD device comprises the large NMOS transistor, resistor 12, and NMOS transistor T2. The large NMOS transistor of such an ESD protection device performs the function of transistor T1 of device 50, by turning on or breaking down when the ESD voltages exceed, for example, -15 volts or +15 volts, respectively, with respect to V.sub.CC or V.sub.SS.
FIG. 1b shows another conventional ESD protection device 51 comprising a resistor 12 and an NMOS transistor T2 with its gate G2 grounded directly to V.sub.SS. Resistor is optional as shown in ESD protection device 52 of FIG. 1c and performs a similar function to that of resistor of device 50. In botch ESD protection devices 51 and 52, NMOS transistor T2 absorbs most of the ESD energy thereby avoiding a large current surge into the input of buffer driver 10 when subject to the ESD test voltages. N-channel transistor T1 of devices 51, 52 operates in a manner similar to transistor T2 of device 50, except that transistor T2, being the only transistor in device 50, has to absorb most of the energy from the ESD discharges. As such, devices 51 and 52 have all the disadvantages of device 50 but are smaller than device
FIGS. 1d and 1e show variations 53, 54 of ESD protection devices 51 and 52, respectively, wherein the gate G2 of transistor T2 is coupled to the output of an inverter 15 whose input is coupled to V.sub.CC. Resistor 12 is optional as shown in ESD device 54 and performs the same function as resistor 12 of device 50. Again, NMOS transistor T2 of ESD protection devices 53 and 54 absorbs most of the ESD energy by providing a current path for the ESD discharge thereby protecting the input of buffer 10. As discussed above, because ESD protection devices 53 and 54 have N-channel transistor T2, they are able to sustain the negative voltage ESD tests without damage by operating in forward biased mode. Devices 53 and 54 are slightly less vulnerable to positive against V.sub.SS discharges than devices 51, 52 because in devices 53 and 54 the voltage level at gate G2 of transistor T2 is undefined since the IC is not powered (i.e. no V.sub.CC voltage is applied) during ESD testing, i.e. gate G2 of transistor T2 is neither coupled to a high or low logic level thereby allowing transistor T2 to partially turn-on.
During the positive against V.sub.CC test, there is no direct current path from source S2 of transistor T2 to V.sub.CC. Hence transistor T2's capacity to efficiently conduct current from this ESD test. is reduced. Nevertheless, devices 53 and 54 are slight improvements over device 50 because the voltage level at gate G2 of transistor T2 is undefined which allows transistor T2 to partially turn on, thereby reducing the proportion of ESD current flow in the undesirable breakdown mode.
FIGS. 1f and 1g show conventional ESD protection devices 55 and 56, respectively. Output ESD protection device 55 has a pull-down NMOS transistor T4 and a pull-up MOS transistor T3, which although shown as a PMOS transistor can either be a PMOS or an NMOS transistor. ESD protection device 55 protects output buffer drivers 20, 21 from electrostatic discharges at an output pad 22. Similarly, ESD protection device 56 protects the input of buffer driver 10 and output buffer drivers 20 and 21, coupled to a tri-state I/O pad 23. Gates G3 and G4 of transistors T3 and Tt, respectively, are coupled to their respective output buffer drivers 20 and 21. Again, resistor 12 is optional and operates like resistor 12 of device 50.
N-channel transistor T4 operates in a manner similar to transistor T2 of devices 53 and 54 as described above, with the same drawbacks. The introduction of transistor T3 coupled through resistor 12 to I/O pads 22, 23 and directly to V.sub.CC, as shown in FIGS. 1f and 1g, respectively, improves the results of the positive against V.sub.CC ESD test by providing a current path from the drain of transistor T3 to V.sub.CC. If transistor T3 is an NMOS transistor, it conducts most of the ESD current to V.sub.CC in the undesirable breakdown mode (transistor T3 is partially on since the input voltage gate G3 is floating, i.e. not coupled to a node having either a high or low logic level). Alternatively, if transistor T3 is a PMOS transistor as shown in FIGS. 1f, 1g, then transistor T3 is able to conduct current to V.sub.CC in the more desirable predominantly forward-biased mode.
Nevertheless, ESD protection devices 55 and 56 each require two transistors T3 and T4 instead of one transistor. In addition, because FET T3 is not coupled directly to V.sub.SS and FET T4 is an N-channel FET, devices 55 and 56 both lack a direct and predominantly forward biased current path from pad 22 to V.sub.SS when subjected to the positive against V.sub.SS ESD test, causing the ESD test current to flow through an indirect and potentially damaging path (not shown) towards V.sub.SS.
Although conventional ESD protection devices 55 and 56 are improvements over ESD protection devices 50 through 54, by providing slightly improved protection from positive against V.sub.CC electrostatic discharges, there is one remaining test i.e., positive against V.sub.SS, the potentially most destructive of the four ESD tests for the reasons discussed above, wherein conventional ESD protection devices 50-56 offer inadequate ESD protection.
Accordingly, there is a need for an ESD protection device that provides good protection for all four ESD tests, in particular the critical positive against V.sub.SS test. Further, such an ESD protection device should also not substantially increase the number of transistors, i.e., the total circuit area.